Making Successful Power Distribution Designs


Why you should take this course:

​This is the popular power distribution design course expanded with more illustrations, exercises and reliability as well as environmental topics. This course is aimed for industry professionals, taught by an experienced industry practitioner who have done many successful high-performance designs. The course tutor has also many years of teaching experience as a university professor.

All delegates attending this course will receive a reference copy of "Power Distribution Network Design Methodologies" by the Course Tutor, Dr Istvan Novak (Originally published by International Engineering Consortium - 15 Jul 2008).

Who is it for?

  • Board design engineers, system designers and power-integrity specialists in the high-speed computing, networking, artificial intelligence, automotive, medical and defense industries, who are interested in a broader and better understanding of power integrity and potential power integrity issues.
  • Managers and engineers who are interested in understanding the simulation and measurement challenges and solutions in power integrity.






The tutor for this course, Dr Istvan Novak, was announced as Engineer of the Year 2020 at the DesignCon event in Santa Clara, Calif. (Jan 30, 2020)

Programme details

Day 1:

  • How power integrity, signal integrity and electromagnetic compatibility interact. You will learn why - as opposed to signal-integrity noise- power distribution noise tends to be very wide band. 
  • Calculating worst-case time-domain power-distribution noise. Reverse Pulse Technique, a very powerful, yet simple methodology to find worst-case time-domain PDN noise response.
  • Models of vias and pads, models of various capacitors and power planes. You will see that for power distribution applications, losses are many times our friends. You will learn why and how.
  • DC drop on power planes; optimization of plane voltage drop - we will demonstrate that 1+1 is not always 2.
  • DC-DC converters in the power distribution network, response time vs. output impedance - you will see live oscilloscope demonstrations of good and bad converter behaviours.
  • Minimizing noise by creating flat impedance response, conditions for smooth impedance profiles. We will show that flattening impedance profile is a very effective way to reduce noise.
  • Bypass capacitor selection: synthesis of 'Multi-pole', 'Big-V', 'Flat' impedance profiles, area capacitors. You will see the strengths and weaknesses of each and we will discuss how to select the solution suitable for your design on a DDR memory PDN example. 
  • Stackup/layout considerations, proper location and placement of capacitors, plane splits and plane stitching. Plane splits in reference planes slow down signal edges, radiate, but most importantly, increase crosstalk among signals crossing it.

Day 2:

  • Time and frequency-domain description of PDN noise - time domain is better suited for low duty cycle rare, but large noise events. Frequency domain is better to identify any periodic noise component.
  • What you need to know about network matrices: impedance, admittance, scattering, and transfer matrices - we will explain why impedance matrix is the good metric for PDN, yet most measurements require S-parameters.
  • Linear network characteristics, time and frequency-domain simulations, moving between the domains - we will show many of the common pitfalls when FFT/IFFT is used to generate PDN response.
  • Simulating and measuring DC drop - we will illustrate the three-dimensional nature of current distribution at DC.
  • High-frequency response, plane modal resonances and their suppression. Plane resonances and plane- capacitor antiresonance increase noise - we will learn three techniques how to suppress these resonances.
  • Designing PDN filters: low-Q transfer functions, lossy ferrites - you will receive a simple design tool, which we will use in the class to show how to design a good PLL filter.
  • Reliability, life-expectancy and thermal design considerations. You will learn how to select components to meet life expectancy, why you should not use an 85-degC rated ceramic capacitor at 85 degree Celsius temperature. How to select fuse ratings to protect against various levels of system issues. We will illustrate why dynamic current balancing is important for reliability. 

Day 3:

  • Measurement solutions for PDN; selecting probes and instruments.
  • Two-port VNA measurements: the two-port measurement is the only usable approach for measuring low-impedance PDN.
  • How to select instruments to do the job without overspending. The little dirty secret of application notes: why many suggest (wrongly!) to measure noise across capacitors.
  • Modelling, simulation and measurement of bypass capacitors, ferrites and inductors: some ceramic capacitors and ferrites exhibit strong dependence on DC and AC bias.
  • How to simulate and measure DC and AC bias effects. Simulating ceramic capacitors at different temperatures.
  • Modelling, simulation and measurement of DC-DC converters - there are a few important DC-DC converter parameters, which are very hard to simulate. You will learn which those are and how to handle them.
  • Modelling, simulation and measurement of vias - you will learn why most blind vias can carry more current than plated through holes.
  • Live measurement demonstration showing the simultaneous measurement of control-loop stability and output impedance.
  • Modelling, simulation and measurement of power planes and systems. Measuring power planes at high frequencies require good connection techniques - you will see case studies when you need 1D, 2D or 3D simulators for power planes.

Attending Your Course 

Further details will be emailed to you two weeks ahead of your course, which will include registration information. 

Please get in touch if you have not received this information within five working days of the course start date.  

In the meantime, you may wish to plan your travel: Travel information

Digital Certification

To complete the course, you will be required to attend and participate in all of the sessions on the course in order to be considered for a certificate. Participants who complete the course will receive a link to download a University of Oxford digital certificate. Information on how to access this digital certificate will be emailed to you after the end of the course.

The certificate will show your name, the course title and the dates of the course you attended. You will also be able to download your certificate or share it on social media if you choose to do so.


Description Costs
Discount package (with Resetting Your Signal Integrity course) £2850.00
Standard course fee (this course only) £1525.00


This course may be taken alongside Resetting Your Signal Integrity Knowledge for a discounted combined fee of £2,850.00. If you would like to opt for this, please select the relevant option after pressing 'Book Now'.

Fees include course materials, tuition, refreshments and lunches. The price does not include accommodation.

All courses are VAT exempt.

Register immediately online 

Click the “book now” button on this webpage. Payment by credit or debit card is required.

Request an invoice

If you require an invoice for your company or personal records, please contact us on the details above.
Please do not send card or bank details via email.


Dr Istvan Novak


Principal Signal and Power Integrity Engineer


Istvan is the Principal Signal and Power Integrity Engineer at Samtec.  He is currently working on new technologies and system designs that enable customers to improve power delivery and increase data speeds beyond 100Gbps.  He is a Life Fellow of IEEE for his contributions to signal-integrity and power-integrity designs, modeling, measurements and simulations. He has 40+ years of experience in high-speed and high-power electronics designs as well as teaching and consulting.

Previously Dr Novak was at Oracle/SUN for 21 years, working on new advanced power distribution design, signal integrity and validation methodologies. He was responsible for the power distribution and high-speed signal integrity designs of SUN's successful workgroup server families. He introduced the industry's first 25um power-ground laminates for large rigid computer boards, and worked with component vendors to create a series of low-inductance and controlled-ESR bypass capacitors.

Dr Novak also served as SUN's representative on the Copper Cable and Connector Workgroup of InfiniBand, and is engaged in the methodologies, designs and characterization of power-distribution networks and CPU packages and has twenty five patents.

He is the lead author of the book "Frequency-Domain Characterization of Power Distribution Networks" (Artech House, 2007) and Executive Editor of the book "Power Distribution Design Methodologies" (IEC, 2008).

In 2020, Dr Novak was announced as Engineer of the Year at the DesignCon event in Santa Clara, Calif. (Jan 30, 2020).

For additional insight into Dr Novak, please read the EDN Network's Profile in Design.


If you would like to discuss your application or any part of the application process before applying, please click Contact Us at the top of this page.


Although not included in the course fee, accommodation may be available at our on-site Rewley House Residential Centre. All bedrooms are en suite and decorated to a high standard, and come with tea- and coffee-making facilities, free Wi-Fi access and Freeview TV. Guests can take advantage of the excellent dining facilities and common room bar, where they may relax and network with others on the programme.

To check prices, availability and to book rooms please visit the Rewley House Residential Centre website.